1. Field of the Invention
The invention generally relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device that includes forming a spin-on-carbon (SOC) film.
2. Brief Description of Related Technology
Semiconductor devices, such as dynamic random access memory (DRAM) devices include more transistors in a limited region to improve integration of the devices. A vertical transistor technology of including memory cells in a small area has been suggested to further improve integration.
In a memory device, a vertical transistor has a gate structure that surrounds a vertical channel. In order to form a surrounding gate, a channel region is formed by a selective isotropic etching process to be thinner than a source/drain region, thereby obtaining an excellent device characteristic. As a result, the vertical transistor can use a limited area effectively. The vertical transistor has been spotlighted in various fields because it is expected to more easily form a smaller-sized transistor.
The vertical transistor may maintain a given channel length, even in reduced device areas and, therefore, may be an effective means to a short channel effect (SCE). Specifically, the surrounding gate structure can maximize controllability of the gate to improve the SCE as well as to provide an excellent operating current characteristic due to a large current flowing area. As a result, the vertical transistor is required to have a thinner and longer structure to improve the integration. However, when the surrounding gate of the vertical transistor is formed, an etching process for isolating a thin and deep bit line may not be formed due to a high aspect ratio.
FIGS. 1a to 1h are cross-sectional diagrams illustrating a conventional method for manufacturing a semiconductor device. Referring to FIG. 1a, a hard mask pattern 15 defining an active region is formed over a semiconductor substrate 10. The substrate 10 is etched with the hard mask pattern 15 as a mask to form a first pillar 20. A spacer 15a is formed at sidewalls of the first pillar 20 and the hard mask pattern 15. The substrate 10 is further dry etched using the hard mask pattern 15 and the spacer 15a to form a second pillar (not shown). A sidewall of the second pillar (not shown) is isotropic-etched to form a third pillar 25 for forming a surrounding gate. A first bit line implant region 40 is formed in the substrate 10 between the third pillars 25. A source/drain region is formed in top and bottom portions of the third pillar 25. A gate oxide film (not shown) and a gate polysilicon layer 30 are formed at sidewalls of the third pillar 25 to obtain a surrounding gate to complete a vertical transistor 50.
Referring to FIG. 1b, a first SOD film 60 is formed over the semiconductor substrate 10, including the vertical transistor 50. The substrate 10 including the first SOD film 60 is annealed at 600° C. The annealing process imparts a rough surface to the first SOD film 60. A chemical mechanical polishing (CMP) process is performed to remove the rough surface. An excessive stress is applied to the vertical transistor 50, which causes the vertical transistor 50 to collapse.
Referring to FIG. 1c, an amorphous carbon layer 65 and a SiON film 70 are sequentially formed over the semiconductor substrate 10, including the first SOD film 60. A photoresist film 75 is formed over the SiON film 70.
Referring to FIG. 1d, the photoresist film 75 is partially etched to form a photoresist pattern 75d, exposing a region between the vertical transistors 50.
Referring to FIG. 1e, the SiON film 70 and the amorphous carbon layer 65 are etched, using the photoresist pattern 75d as a mask, to form an amorphous carbon pattern 65d and a SiON pattern 70d. The amorphous carbon pattern 65d and the SiON pattern 70d are thereafter used as a hard mask pattern for forming a bit line isolating trench.
Referring to FIG. 1f, the first SOD film 60 and the substrate 10 under the first SOD film 60 are etched, using the SiON pattern 70d and the amorphous carbon pattern 65d as a mask, to form a bit line isolating trench 80. The first bit line implant region 40 is divided, which becomes a first bit line 40a. Thereafter, the SiON pattern 70d and the amorphous carbon pattern 65d are removed.
Referring to FIG. 1g, a second bit line implant process is performed on the bottom portion of the first bit line 40a to form a second bit line 85. As shown in FIG. 1h, a second SOD film 90 is filled in the bit line isolating trench 80 for a subsequent process.
As mentioned above, when a bit line is formed in a vertical transistor, the bit line is filled in the bottom of the transistor. As semiconductor devices become more highly integrated, the gap between vertical transistors becomes narrower, requiring use of a SOD film having an excellent gap fill characteristic as a sacrificial film for forming the bit line trench. The SOD film, however, requires an annealing process at a temperature greater than 600° C., and subsequent CMP to remove the surface left by the annealing process. While the SOD film is formed, an over-stress is applied to the vertical transistor, and the vertical transistor collapses under the stress. As a result, the yield of the semiconductor device is reduced, and an unnecessary process is performed.